An Updated Memory Module : Part 3a - Main Board Build

We have boards!

02/08/14, AM: Main boards arrived yesterday!

A little slower than usual (just under 3 weeks, vs just over 2 weeks in the past), but I'm not going to complain. I'll reserve my complaining for the idiot who ordered the wrong voltage regulators (TO-263 vs DPAK/TO-252); he has been given the task of finding the correct regulators on a Saturday morning. Not easy in a world where the main electronics hobby chain stocks more farting toys than surface-mount components…

For a change, I think I'll keep updating this post as I build and test the board - you don't want to dig through multiple posts, and I don't want to make them.

More when I get back from my search…

Bottom side, with 0805 caps at C20/C22 & missing L4/L6

02/08/14, 9:00 PM:  I don't recall drinking when I ordered the parts for this, but I must've been! I've almost finished assembling the bottom side of the board, and so far the mistake count is:

1. Ordered 5v regulators in the wrong package - I mentioned this earlier, and luckily I managed to get some in DPAK from a local trade counter this morning.
2. Forgot to order 470pF caps in 1206  - luckily I had some in 0805 left over from another project, which I've squeezed in.
3. Ordered the 1.5μH inductors (0805) for the VFO filter in wirewound, not multilayer - not a great problem since the filter is probably unnecessary to start with (or at least grossly overdesigned), but they're a pain to solder due to the plastic shroud hiding the terminals.
4. Forgot to order 5.6μH inductors for the same filter.

Looks like I'll have to order a few more parts on Monday…

03/08/14, 4:30 PM: Had other things to do this morning, and more to do later, so I haven't had much of a chance to work on the board. But I managed to assemble and test the difference/offset amp (for the fine tuning) and the comparator (for the frequency counter). And yup, another dumb error - I left a resistor out of the difference amp circuit and had to bodge it in.

That's it for the easily-testable-as-I-go-along bits. Testing the rest requires the micro to be programmed, so it'll have to wait until it's almost done.

05/08/14, 11:00 AM: Yesterday I assembled enough of the micro that I can program it with the bootloader. Only problem is the custom bootloader (for 20MHz & external clock) isn't compiling…

Bootloader installed, chasing upload bug!

05/08/14, 11:00 PM: Finally - got a bootloader & quick test sketch installed! Problems were due to some odd issues I had compiling & loading the custom Arduino bootloader required for 20MHz operation on a non-P ATmega328 (gave up and loaded a pre-compiled one using the -F switch in avrdude), a dud FTDI/serial cable (replaced with a Freetronics USB-to-serial adapter I bought on a whim from the fart-toy shop last time I was there), a potential hardware bug / design error (the serial adaptor doesn't reset the ATmega to start the sketch uploading, though the reset button & ICSP connector work fine; I've yet to look into why), and the general stupidity/shittyness of the Arduino environment and its documentation…

07/08/14, AM: Assembly is almost complete, with only a couple of coupling resistors / caps between different parts of the circuit left out for testing purposes. Later today I'll finish the testing, modify the demo software to suit the new hardware, and give it a go! Oh, and I'll post some more pics too…

07/08/14, PM: Still working on programming/testing the DDS chip. Not done yet, but I discovered by accident that some functions of the AD5930 (e.g. burst mode) work on the AD5932 (where the equivalent config bits are marked as 'reserved'). I wonder if they're the same die that have failed specific tests, or if it's simply product differentiation?

After I've got the whole circuit tested & working, I'll look into whether the continuous sweep modes ('triangular-sweep' and 'saw-sweep') of the AD5930 work in the AD5932. They might make some interesting features possible - e.g. does bounded, full-band, or full 0-30MHz scanning interest anyone?

(Damn, I should've arranged things to include a digital input pin or two on the external I²C connector. That way a future add-on could've plugged into the FRG-7700's ACC connector and monitored the AGC signal to pause scanning. Oh well, I guess I can always use one of the ICSP pins…)

10/08/14, PM: I'm reluctantly coming to the conclusion that the AD5932 isn't really suitable for this purpose. Due to the typical output dropoff with rising frequency inherent with DDS, with a 20MHz clock the signal is useless above a few 10's of KHz. That's actually much worse than I anticipated (I figured it'd still be good up to 4~5MHz - and I'm still a little baffled as to why it's not).

Which is annoying.

That said, thanks to my overkill with the output filter, it's not a show-stopper. The square wave output from the DDS is still good at the 2.5-3.5MHz needed for the VFO, and the filter will clean that up just fine to a good sine wave. It certainly won't be any worse than the original memory unit, which also generates a square wave…

But I really want to do this properly before I release it for general use, so once I get this version built I'll have to work it all out. Maybe just sticking a socket on board for one of the cheap DX/eBay AD9850 DDS modules is the easiest way…

(Some good will come out of it though. The AD5932 is a little tricky to communicate with and, although many have asked, there's no Arduino library for it. I'll release it when I get it done…)

11/08/14, AM: No, that's bullshit - there's no way the signal level should drop anywhere near that much due to sin(x)/x. Something else is going on…

11/08/14, PM: Figured it out! I'd made a mistake on the silkscreen and swapped the labels of two capacitors (18pF across the DDS output, & a 0.1μF supply bypass cap). And, of course, 0.1μF @ 3MHz is something like half an ohm…

DDS simulator results

12/08/14, PM: Still waiting for the inductors to finish off the VFO output filter (they were on backorder, and are shipping to me alongside some stuff that needs to come by road). Until then I'll play with the software; in the meantime, here's a couple of pictures that might be interesting.

The first is the unfiltered DDS output at 2.5MHz, as simulated by Analog Devices' ADIsimDDS online simulation tool. While it might look ratty if you're expecting a pure sine wave, it's actually pretty good - the majority of the distortion is due to the high image component in the signal (20MHz DDS clock - 2.5MHz generated signal = 17.5MHz image, plus others as shown in the spectrum plot to the left). There's no getting around that; it's a fact of life of DDS synthesis, and all you can do is keep the images far enough away from the desired signal that they can be filtered out. Hence the massive overkill of the 5th-order Chebyshev bandpass filter I incorporated into the design…

Actual DDS signal (after amplification)

The second is the actual output of the DDS, after amplification and before filtering. Ignoring the shitty photo and screen reflections, it's pretty similar to the simulation. And count the 'extra' superimposed peaks per cycle - 7 * 2.5MHz = 17.5MHz, just as predicted…

It's always nice when you can see theory work, isn't it? ;)

And that's where things sit at this point. As I said, I'll keep working on the software (initially an Arduino library for the AD5932 as mentioned earlier, followed by tying it all together into a working memory unit) until the inductors for the filter turn up later this week. If everything goes to plan I'll post some more photos of the completed unit and installation before the weekend.

14/08/14, PM: The inductors for the filter arrived today, and I finished assembling the board. For anyone who may have doubted the noisy jagged DDS signal above could ever be turned into a nice clean sine wave, here's the proof:

DDS output after amp & filter (updated pic)

Looks pretty darn good to me!

No, it's not 100% perfect - it doesn't show up clearly in the pic, but there's some very slight distortion on the curve just before the peak/trough. But compared to the front-panel VFO (which has several obvious distortions, from asymmetrical flattening to strong higher-order harmonics, at various places across its output range) it's practically golden. In practice that doesn't matter t-o-o much in a set like this - you could probably get away with a square wave VFO without affecting overall performance too greatly, although all the distortions add up - but it's nice to know that my circuit should give better performance than the original…

Almost done! Tomorrow I'll post up some pics of the completed board, then it's full steam ahead with the software!

15/08/14, PM: Here's some pretty pictures as promised…

Main Board 'topside'

The first one is the topside of the board, amost complete except for R22 (which connects the fine-tune opamp with the micro) - I might need to tweak that value. On the top-right is the AD5932 DDS chip (IC5) and associated components, with the 20MHz oscillator (XO1) to its lower-right. Next is the ATmega328 micro (IC4), with the associated in-circuit serial programming interface to its top-left. Below the micro is IC6, a 32k x 8 bit EEPROM which will be used as the actual memory.

On the lower-left is IC3, an LMV761 comparator used to convert the radio's VFO into a square wave before feeding it to IC4 for counting. And in the lower-right corner is the +5v regulator, IC1, supplying everything on the top side of the board.

The upper red button and the LED below it are both are connected to I/O pins of IC4. I intend to use them for initial calibration / setup and other general-purpose use. The lower red button is resets the micro. To the right of that, SV5 is a standard Arduino serial "FTDI" connector for uploading software. SV6, to the left of the reset button, brings out the I²C buss for use with other potential peripherals (direct-entry keypad & display, anyone?). SV4, to the lower-left of SV6, is a jumper block to select the input to the frequency counter (e.g. for calibration).

Main Board 'underside'

The next picture is the underside of the board. SV1 (middle) and SV2 (lower edge) plug in to the interface board - SV2 brings 11v power, M/MR buttons, and the fine-tuning and front-panel VFO signals from the radio to the main board, while SV1 connects the I²C buss, associated signals, and +5v power to the interface board.

At the top-right is a simple 2-transistor amplifer for the DDS signal - this has 6-7dB of voltage gain and provides a low (~30ω) impedance output to match the filter & radio. The filter itself is below it, on the bottom-right of the board.

The components along the left-hand side are associated with the switches and serial port on the top side of the board.

And finally, just left of centre and above SV2, is IC2, a LM321 opamp. Along with its associated components it forms a difference/offset amp to convert the 1.5v-6.5v signal from the fine tune control to a 0-5v signal suitable for the DAC in the ATmega328.

Oh, and I know, the whole thing needs to be cleaned to wash the excess flux away…

Damn! I forgot; I was going to put a ruler or something beside it for scale. The whole thing is 50mm wide and 90mm high. When fitted with its metal cover it'll be the same height as the original MU-7700, but about ¼ the width…

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On a completely different topic: Just for the sake of completeness I made a few calculations & measurements of the DDS output frequency:
Desired frequency = 2.5MHz:

• DDS programming word (in hex) : 200000
• DDS programmed frequency: 2.5MHz (an error of 0ppm)
• DDS measured output frequency: 2.50003MHz
• Measured error: 12ppm

Desired frequency = 3.5MHz:

• DDS programming word (in hex): 2CCCCC
• DDS programmed frequency: 3.49999905 (an error of 0.27ppm)
• DDS measured output frequency: 3.500041MHz
• Measured error: 11.71ppm

So, without any calibration, the prototype has a frequency error of ~±12ppm, or 30~40Hz. Given that the 20MHz oscillator used is spec'd at (IIRC) ±50ppm, I think that bodes well for the ultimate resolution of the unit. Although it probably won't make it into the initial software release, as I mentioned above there's provision on the board for calibration of the software frequency counter - which can then be used to correct the DDS tuning for oscillator variation. I also estimate the fine-tune control to have better than 20Hz resolution, though that's a little more up in the air - it's somewhat dependent upon the accuracy of the radio's internal 11v rail, which will vary from set to set. Nothing I could do about that, sorry…

So, fingers crossed, the memory unit should be able to tune with an accuracy of ~10Hz or so, and the fine tuning should be able to tune in steps of 10-20Hz. For comparison, the later FRG-8800 tuned in 25Hz steps, and it wasn't until the even later FRG-100 that 10Hz tuning steps were available.

And I think I'll leave it at that for construction details. Next stop … software…

18/08/14, 2:30 PM: No, I think I'll post one last set of pictures just to show how it all comes together...

The radio cabling connects directly to the interface board.

The interface board replaces the original cover plate.

Close up of the installed interface board.

The main board plugs into & piggybacks on the interface board.

Close up of the main board (ribbon cable is for programming).

Currently I'm working on the software to test out the hardware. So far everything's working properly, although the frequency counter routine needs some tweaking to deal with the higher clock speed. I'm particularly impressed by the fine-tune control; it should be possible to fine tune across ± 2kHz in steps of ~5 or 10Hz (although the accuracy of those steps won't be in exactly round Hz figures...)