An Updated Memory Module : Part 1 - How the hell does it work?

Have you ever looked at the memory module circuit?

I mean, really looked at it?

It's actually pretty trick, and a nice example of how analogue & digital electronics were being married in the 70's. It's also deceptively simple in what it does, and only slightly more complicated in how it does it.

And I'm designing a new one from scratch…

The key to understanding how it works is in knowing, at a fairly simple level, what it's got to do. Basically it has to:

1. Know what memory position you want to use to store/recall a frequency. This comes from the Memory position switch at the top-right of the front panel.
2. Know which 1MHz band you're tuned to, and a couple of settings associated with that e.g. the front-end filters. This comes from the main Band switch on the bottom-right.
3. Know what frequency within the band you're tuned to. This comes from the VFO (Variable Frequency Oscillator), aka "The Big Tuning Knob On The Front".
4. Be able to play out #2 & #3, on demand, from #1.

Simple, huh!

Actually, it is. Those 4 points are just about the most comprehensive explanation of the memory unit I've even seen anywhere. You could almost build your own memory unit without knowing anything else. Of course, the devil is in the detail of how it does it, but still…

(Update: Of course, after figuring it all out for myself and writing the first 2 posts of this series, I stumbled across John Mills' website and his old R&EW article where he outlines how the memory unit works. Oh well, I figured someone had to have gotten there before me…)

So let's look at the "how" in a bit more detail. Old-school analogue radio types: don't get put off by the fact the circuit shows nasty digital things like memory chips and counters and logic gates and… Seriously, this design dates from the late 70's, and digital was much simpler back then. If you can understand that divider chips divide, counter chips count, and memory chips remember things, then you'll follow it just fine…

1. The memory position switch comes in on pins 5-12 of connector J02. These pins are switched to +5v (fed from pin 4 of J02) in a pattern which describes the selected memory position.
• Hint: don't try to figure out the pattern - it doesn't seem to follow any logic, and I'm not even sure my set matches the schematic! Just accept that it "is"…
• You might also realise that 8 pins can carry far more than 12 switch positions; up to 2⁸ = 256. That's the basis of the old 256 memory mod by Nicholas (JN18), which replaces the 12 position switch with a couple of binary-coded hex switches.
2. The band (0-29MHz) comes in on connector J03. It's a very similar deal to the memory position - pins 4-9 are pulled high (+5v) in a pattern to describe the band (0-29MHz; the 'ham band' locations on the switch re-use the matching MHz band pattern).
• There's also some extra information on other pins - the pattern on pins 1-3 describes the front-end antenna filter for that band, and the pattern on pins 10 & 11 describes the VCO (Voltage Controlled Oscillator; the set's "main" oscillator) setting for each band
3. The VFO (tuning) frequency comes in on J06. At this point it's an analogue sine wave signal - about 2/3 of the memory unit circuitry is dedicated to either counting the frequency of this signal, or synthesising a substitute signal based on that count (both of which I'll explain later). The other 1/3 is …
4. The memory itself. Those μPD5101LC's RAM chips are odd beasts by today's standards - the 8 bit address buss (AI) is fair enough, but the 4 bit words and separate Data In (DI) and Data Out (DO) lines are unusual. Luckily, that makes the whole thing really easy to follow…
• The 8 lines from the memory switch are connected to the 'address' lines of all of the memory chips (Q30-Q35). This controls the location in each memory chip where the other data (band, filter, VCO, & VFO frequency) is stored. It doesn't really matter that there's no logic to the pattern on those lines - as long as each switch position has a unique pattern.
• The 11 lines from the band switch - 6 for the band, 3 for the antenna filter, 2 for the VCO setting - are connected to the Data In lines of Q33-Q35.
• Another 13 lines from Q26 & Q27 (which form part of the frequency counter section) are connected to the Data In lines of Q30-Q33.

The upshot of all that is that, when triggered by pushing the "M" button on the front panel, the information for switching the radio and generating a new tuning signal is stored in the memory chips.

When the "MR" button is pressed it disconnects the band switch and VFO in the main radio, and triggers the memory chips to play out the contents of the selected address on the Data Out lines. The band/antenna/VCO parts of this (from Q33-Q35) are fed out to the radio on J04 & J05 (where they mimic the original switch), while the VFO tuning signal count (from Q30-Q33) is presented to the part of the memory unit which recreates the original VFO tuning frequency - which, ultimately, is fed back out the way it came in (on J06).

So really, the only things left to explain are:

• The frequency counter: Q22-Q29 form a frequency counter with a binary-coded decimal (BCD) output. The incoming VFO tuning signal comes in on J06 at the top right of the circuit, along the wire marked "VFO In/Out", and is amplified (and probably squared up) by Q28 & Q29. Meanwhile, an 800Hz clock signal from the main set is fed to Q22, where it is divided down to (amongst others) a 100Hz clock. The two signals - the VFO signal from the collector of Q29, and the 100Hz clock from pin 6 of Q22 - are gated by a NAND gate (1/3 of Q24), which feeds a divide-by-10 counter (Q25) followed by a pair of dual BCD up-down counters (Q26 & Q27). The outputs of those counters is a 13-bit BCD number (4 bits per digit) representing the frequency - 4 bits for the 1kHz digit, 4 bits for the 10kHz digit, 4 bits for the 100kHz digit, and 1 bit for (2 or 3) MHz - which feeds the Data In lines of Q30-Q33.
• The "replacement" VFO: This makes up pretty much the whole top-third of the circuit diagram (Q01-Q21, and Q36), and is devilishly hard to explain. The heart of it is another VCO (Q01 & Q02), which seems to free-run at ~16x the nominal VFO frequency (i.e. ~48MHz). This signal is divided down by a fixed amount by Q07, and by a variable amount (based on the original stored VFO frequency) by Q09-Q12. This much-divided signal is then fed to one input of Q19, a Phase-Locked Loop (PLL), while the other input is a 16kHz signal generated by dividing down (with Q21 & Q20) a 16.384MHz crystal oscillator. The PLL 'compares' these two signals, and the error voltage - expressing the difference between the two - is used to adjust the frequency of the original Q01/Q02 oscillator via varicap diodes D01 & D02, which quickly gets pulled into to running at 16x the stored VFO tuning frequency. This is then is divided down by 16 in Q04, and that forms the tuning signal from the memory module.

But for gawd's sake, don't quote me on any of that last explanation - I could be totally wrong! It's enough to know that the data from RAM is used to tune the Q01/Q02 oscillator in line with the originally stored frequency…

Especially since I've already got a much simpler replacement breadboarded and working. A microcontroller reads the switch inputs, and drives the band/VCO/antenna filter control outputs, via a couple of I²C port expanders. It also counts the frequency of the front-panel VFO and, when in memory recall mode, drives a DDS oscillator to replicate the VFO tuning signal. At the moment I'm re-writing the basic software - I started with a MSP430 development board, but moved to an Arduino / Atmega328 to make it easier for others to build and hack - while I think about how to do the final design, what features can easily be added, etc.

Definitely more to come…